This invention relates to the field of computer aided design of very large scale integration (VLSI) semiconductor circuits and more particularly to the design and production of customizing masks for universal arrays.
Universal array integrated circuits (ICs) are used to test IC designs and for production of ICs. One such universal array is the 800 gate automated universal array or AUA developed by RCA Corporation in cooperation with the Department of the Army under a series of contracts. A plurality of these AUAs are fabricated on a semiconductor wafer. Each AUA comprises an interior row region containing many parallel rows of identical basic units each containing four semiconductor devices. This interior basic unit row region is surrounded by a rectangular annular region of peripheral devices and contact pads for the connection of external wires to the IC. The rows of basic units are spaced apart by wiring roadbeds. These roadbeds contain wiring channels which run parallel to the length of the basic unit rows and wiring lanes which run perpendicular to the length of the basic unit rows. Each wiring lane comprises an aligned series of five tunnels which have their adjacent ends spaced apart. All of the tunnels adjacent to one edge of a basic unit row comprise a tunnel rank. The next adjacent set of tunnels comprise another tunnel rank and so on. Each tunnel rank has three of the wiring channels disposed thereover.
An electrically insulating layer covers both the semiconductor devices and the tunnels except at predetermined contact points where it is desired to have electrical contact between a semiconductor device or a tunnel and an overlying, conductive, metallic customizing layer. The customizing layer covers an entire major surface of the semiconductor wafer and is initially in electrical contact with the contacts of all the semiconductor devices and tunnels. To customize this universal array semiconductor wafer into a plurality of integrated circuits having a desired set of electrical characteristics the customizing conductive layer is coated with photoresist and exposed to activating radiation through a custom patterned mask. The custom mask pattern causes the activating radiation to protect those portions of the conductive material which are needed to interconnect the semiconductor devices and tunnels into the desired IC, while leaving unprotected the remaining portions of the customizing conductive layer. The unprotected portions of the customizing layer are removed by etching and the wafer is passivated to prevent environmental damage to the ICs. The completed wafer is tested and diced to provide a plurality of individual ICs all having the desired characteristics.
Where a tunnel in one tunnel rank is to be connected to a tunnel in the next tunnel rank, it can be connected to the aligned tunnel in that next rank or to either of the tunnels adjacent to that aligned tunnel.
The use of a single conductive layer to convert a stock, pre-processed, AUA wafer into a plurality of the desired custom ICs enables rapid completion of the desired ICs once the customizing mask is completed. It is possible to convert a stockpiled wafer into custom ICs in 24 to 48 hours.
Because hand design of customizing masks for these arrays is prohibitively time consuming and expensive, an AUA automatic placement and routing system developed by RCA Corporation is used to automatically design the customizing mask. This system, like the array, was developed by RCA Corporation in cooperation with the Department of the Army under a series of contracts. The software for this system is available in source code form from the Army's Electronics Research and Development Command (ERADCOM), Fort Monmouth, N.J. for use on government contracts. That software is known as the AUA or 800 gate AUA program, version 1.5 and is incorporated herein by reference. This computer aided design (CAD) system can produce a customizing mask for this AUA from a specification of the desired IC in terms of logic gates or "logic cells" selected from a set of available "logic cells" and the connections needed between those "logic cells". The term "logic cell" refers to the one or more basic units which when interconnected by customizing conductors form a logic gate such as an AND gate, OR gate, Flip Flop, etc. This CAD system accepts such a specification of the IC and generates a specification of a mask pattern which can be used to pattern the customizing conductive layer to convert a stock 800 gate AUA into the desired custom ICs. This is done through a process involving automatic assignment of logic cells to basic unit rows of the universal array, automatic placement of assigned logic cells along the basic unit rows and automatic routing of customizing conductors. The resulting mask specification is used to control a mask generating system which converts that specification into the physical pattern of the mask. Thereafter that mask is used in a photoetcher to customize a universal array wafer into a number of the specified ICs.
The computer aided design system must ensure that 100% of the customizing conductors are routed automatically in order for its mask specification to be directly convertible to the final mask used to pattern the customizing layer.
Semiconductor area is wasted if a routing system must restrict an IC design to actually using (connecting into its circuit) only a relatively low percentage (such as 60% or 70%) of the universal array's basic units. Some placement and routing systems must impose such restrictions in order to ensure the routing system's ability to complete the routing of 100% of the connecting conductors. It is desirable that the automatic system be able to complete 100% of the routing in circuits which use high percentages (&gt;80%) of the gates which are available in the universal array.
The AUA automatic placement and routing program cited above is capable of routing 100% of the conductors in the 800 gate AUA to which it applies, even when as many as 90% or more of the basic units are utilized in a random logic circuit.
That AUA automatic placement and routing software employs a routing grid in which each point on the grid is defined by a pair of x and y coordinates. These grid points correspond to physical locations on an actual AUA chip. The grid points are spaced apart in accordance with the design rules of the chip as to conductor width and spacing. Each electrical contact between the customizing layer and a logic cell pin device or tunnel contact is located at a grid point. In addition, each location where a conductor may run can be defined in terms of grid points.
Two different routing techniques are used. One of these is direct routing. In direct routing, the process checks each route in a specific, limited set of possible routes to see if one of those routes is available for the conductor being routed. These routes follow straight line segments which extend parallel to either the x-axis or the y-axis of the grid. The router selects the first one of these routes which is available as the route that conductor will take. If none of those routes is available, then the direct routing process can not route that conductor within the set of routes checked. The availability of a route is determined by checking each grid point on it to see if it is available. A grid point is available if it is not occupied by a conductor which is part of a different node. A node is a set of pins of active basic units all of which must be connected together by conductors and those connecting conductors. All of the conductors and pins of a node are at the same electrical potential.
The other of these routing techniques is pathfinding routing. In pathfinding routing, the search for an available route begins at one of the pins to be connected (the source pin) and works toward the other pin (the sink pin). This search technique checks each grid point which is adjacent to the source pin to see if it is available for the routing of the conductor being routed. All of those grid points which are available are included in an array of available grid points. A grid point is available for the routing of a conductor if it is in the region then allowed for the routing of that conductor and is not occupied by a conductor in a different node. Those grid points which are adjacent to the source pin and available are given the number 1. This process is repeated for each of those available grid points while treating those grid points as source pins. Available grid points adjacent to a number 1 grid point are assigned the number 2. This process is repeated until the sink pin grid point is reached. Then a route for the conductor is determined by tracing the numbers assigned to grid points in a decreasing order from the sink pin to the source pin. In assigning numbers to grid points, the use of some grid points can be discouraged by including a penalty in the number assigned to that grid point by giving it a number which is more than 1 higher than the number of the grid point from which it was reached. Such penalties effect the way in which the route is established during the back tracing of the route which has been found. If there is an available route within the allowed routing region, then this pathfinding process will find it.
In the latter stages of its routing process this AUA software uses a rerouting process in order to increase the number of conductors which it can route. A rerouting process is one which tests each conductor on a grid point by grid point basis to see if that conductor or part of it can be moved over into a different wiring channel which has a lower priority. The priority of wiring channels is established so that those which are located farthest from tunnel contacts and cell pins are filled first. Where possible, the rerouting process moves already routed conductors into lower priority wiring channels to make wiring channels adjacent to tunnel contacts and cell pins available for further routing.
Today universal arrays are desired with 2500 or more equivalent logic gates. The design of such a large universal array in a manner in which it is still customizable by a single conductive layer which is automatically designed is a major challenge. Such an array design is the subject of the patent application entitled, VARIABLE GEOMETRY AUTOMATED UNIVERSAL ARRAY, by Richard Noto, Ser. No. 474,511, filed Mar. 11, 1983, now U.S. Pat. No. 4,568,961, which is assigned to the present assignee. That Application is incorporated herein by reference. Design of a computer aided design system capable of customizing such a large array in an efficient manner is another major challenge. The present invention provides an automatic routing system which is capable of efficiently routing the conductors of the single customizing layer of that large universal array. The design of that array and this software are interrelated.